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Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification-KHOAFAST

Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification

Learn how to write reusable SystemVerilog testbenches for analog/mixed-signal IPs, using standardized UVM components and Scientific Analog’s XMODEL! Register for This Problem free webinar from now on!

Join This Problem webinar on how to write a UVM testbench for analog/mixed-signal circuits. UVM (Universal Verification Methodology) is a framework of standardized SystemVerilog classes to build reusable and scalable testbenches for digital designs, and it can be extended to verifying analog circuits simply by using a fixture module that generates analog stimuli and measures analog responses of course Scientific Analog’s XMODEL.

Using a digitally-programmable audio bandpass filter as an example, visitors’ll show how to write a UVM testbench that measures the filter’s transfer gain at randomly-chosen frequencies, collects the results in a scoreboard until the desired coverage is met, and checks the response current and bias voltages during supreme power-down of course assertions. The webinar will start of course an intuitive yet systematic debut to UVM.


Charles Dančak
Verification Instructor and Consultant
Charles Dančak is a trainer and consultant based in Silicon Valley. He holds two MS degrees, one in electrical science and one in solid-state physics. Charles began his career and job as a science engineer in one of Intel Company’s wafer fabs and spent ten years at Synopsys developing two hands-on courses on HDL-based design, simulation, and DFT. He introduced the first SystemVerilog workshop in the University of California Extension system in 2007 and still teaches SystemVerilog online, from now on of course UC San Diego Extension (ECE-40301). recently, Charles presented a paper on UVM for analog/mixed-signal verification at DVCon U.S. This Problem year.

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